The disclosure relates generally to methods and apparatus for providing reduced power consumption in devices and, more particularly, to processors and systems that employ dynamic voltage and frequency scaling systems for power saving operations.
The evolution of modern processor architectures, in conjunction with technology scaling, has produced processors with higher performance to meet today's increasing computational demands, and also helped make power efficiency one of the paramount design concerns and objectives for a wide spread of enterprise-class and embedded processors. In addition to saving energy, proper reduction of power consumption can lead to dramatic benefits in reducing thermal hot spots and the cost of chip-cooling. To this end, dynamic voltage and clock frequency scaling (DVFS) has become a key avenue for achieving power efficiency via adjustment of the operating voltage and frequency of processors in runtimes for devices such as web servers, smart phones, tablet devices, laptops and other devices.
A body of research has been devoted to DVFS, for instance, through heuristic techniques that are geared towards ensuring processor utilization. However, one central challenge in developing DVFS schemes is to balance two competing objectives: maximizing of power saving and guaranteeing tight performance. The latter is particularly critical for latency-sensitive applications that require a high-degree of quality of service (QoS).
Real-time requirements in devices can be dictated by applications that are executing; such as in the context of a smart phone, watching video requires, for example, a processor to generate frames of video for display wherein some frames can require more computations than others. For example, certain portions of video may contain action portions and others may have still landscape images during a movie and the video processor needs to adjust its processing speed to accommodate outputting the appropriate pixel information at the appropriate time. Workload for the processor, which may include multiple cores, for example CPUs or any other suitable processor, utilize streams of instructions.
For other systems such as web servers, power reduction is very important particularly with large numbers of web servers. As known web servers may include multiple processors (for example, they each include multiple CPU cores) that wherein a web server may be required to send the same web page or content to thousands of users or may be required to send differing web pages to multiple users requiring huge variations in workload requirements.
Previous heuristic methods usually design the power saving control algorithms for specific workload inputs. However, because of the random nature of the actual workloads, these control algorithms may not achieve satisfactory performance in terms of real-time or QoS metrics.
Accordingly, a need exists for improved power saving methods and apparatus.